The rise of high definition and 3D media, the vision of hyper-connectivity, and the shift toward cloud computing have prompted the need for gigabit wireless communication systems. However, implementing high data-rate systems poses a number of engineering challenges. One of the main challenging problems is the design of a high throughput error control scheme.
Low density parity check (LDPC) codes are channel codes used in forward error correcting (FEC) schemes. LDPC codes are well known for their good performance and have received a great deal of attention in recent years. This is due to their ability to achieve performance close to the Shannon limit, the ability to design codes which achieve high parallelization in hardware, and their support of high data rates. Consequently, many of the currently active telecommunication standards have LDPC codes in their physical layer FEC scheme.
As data rates in modern communication systems and battery-powered mobile communication and computing devices usage increase, low-power hardware design has become more important. As a result, there is continuing work in the area of improving the power-efficiency and throughput of LDPC encoding and decoding hardware.